hex - How to initialize parameter array in verilog? -



hex - How to initialize parameter array in verilog? -

how can 1 initialize parameter type array in verilog each of members 32 bit hexadecimal notation numbers? have tried next gives me syntax error.

parameter [31:0] k[0:63] = {32'habc132, 32'hba324f, ...};

i'm using latest version of iverilog compiling.

on eda plyground next illustration works using modelsim 10.1, file has .sv extension, causing interpreted systemverilog:

module test; parameter [31:0] k [0:1] = {32'habc132, 32'hba324f}; initial begin $displayh(k[0]); $displayh(k[1]); end endmodule

if setting systemverilog not work or not available simulator suggest including syntax error in question.

parameters hex verilog

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