Disabling interrupt with the ARM GIC (global interrupt controller) -



Disabling interrupt with the ARM GIC (global interrupt controller) -

i have specific requirement nee disable device interrupt specific period without affecting other interrupts(code running on arm processor). arm document pointed gic registers (related enable, disable , clear interrupts) of arm banked registers, there 1 per cpu interface. banked registers accessible designated cpu , controls cpu's ppi , sgi interrupts only.

what mean? if disable specific interrupt writing gic register, disabled on core or on cores?

there 2 register sets gic; banked per cpu set , distribution (also distributor) scheme global gic. link above, irqenset0 per-cpu register banked (again) , handles ppi , sgi interrupts cpu. irqenset1 list of global interrupts , these maybe disable. distribution (also distributor) can target interrupts cpu.

arm has many different names these registers , different versions of gic. concepts same of them. there set of registers not banked per-cpu , these command things globally including disabling interrupts scheme wide. reader competent plenty find , read specific controller documentation soc.

what mean? if disable specific interrupt writing gic register, disabled on core or on cores?

ppi - peripheral private interrupt. example, per-cpu timer in smp systems. sgi - software generated interrupt. known ipi on other systems. allows signaling 1 cpu cpu. (ipi inter-processor interrupt).

these interrupts create sense each , every cpu. however, hardware ethernet, spi, video, can bus, i2c, adc, etc. scheme global.

for distributor registers, global interrupts have read/write enable/disable. registers per-cpu read-only in distributor , indicate interrupt present. other set of registers (per-cpu) normal mechanism enable/disable interrupt per-cpu. software should have inter-lock (semaphore) when accessing distributor global system. alternatively, elected or boot cpu utilize distributor. per-cpu registers banked core may perform read-modify-write without worrying race conditions.

reference: arm generic interrupt controller - architecture specification, may require registration.

arm

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