verilog - The difference between @(a==1) and @(posedge a) -

verilog - The difference between @(a==1) and @(posedge a) -

in non-synthesizable code, difference between:

@(a==1);

and

@(posedge a);

are behaving same?

the next illustration (on eda playground) shows not same :

module test; logic = 1'b0; initial begin #100ns <= 1'b1; #100ns <= 1'b0; #100ns <= 1'b1; #1000ns $finish; end initial begin @(a == 1'b1) $display("%t : == 1 (1) %b",$realtime, a); @(a == 1'b1) $display("%t : == 1 (2) %b",$realtime, a); @(a == 1'b1) $display("%t : == 1 (3) %b",$realtime, a); end initial begin @(posedge a) $display("%t : posedge (1)",$realtime); @(posedge a) $display("%t : posedge (2)",$realtime); @(posedge a) $display("%t : posedge (3)",$realtime); end endmodule

which displays

100 : posedge (1) 100 : == 1 (1) 1 200 : == 1 (2) 0 300 : == 1 (3) 1 300 : posedge (2)

@(posedge a) unblocks on true transition 1 x/z/0. @(a == 1) unblocks when true on alter in either before or after change.

bit ?

when ideclared bit can hold 0 or 1, 2-state not 4-state (0,1,x,z). hence posedge can 0 -> 1 transition. in modelsim 10.1 not alter behaviour of example. aldot (op) made observation @(a==1) behaves same @(a).

verilog system-verilog